The provocation is unit cost. On September 13, 2022, the Massachusetts Institute of Technology was granted US11444027B2, “Wafer-scale satellite with integrated propulsion and attitude control,” classified in H01L 23/5286 — notably the semiconductor-packaging art, not the spacecraft art. That classification is itself the thesis: build the satellite like a chip.
Satellite cost has historically been an artisanal problem — small numbers of complex spacecraft, each expensive. The semiconductor industry took the opposite path: enormous volumes at vanishing per-unit cost via wafer-scale fabrication. A satellite built on a wafer borrows that economic logic, integrating propulsion and attitude control onto the same fabricated substrate so that producing one more is closer to printing a chip than building a spacecraft.
For the business desk, the interesting variable is the cost floor this implies. If constellation satellites could be fabricated at semiconductor volumes and prices, the per-unit cost that today gates constellation size could fall by orders of magnitude. That would change which business models close — a swarm of ultra-cheap satellites supports applications no expensive-satellite constellation can afford.
The disciplined caveat: this is a university patent describing a radical architecture, and the gap between a wafer-scale concept and a flight-qualified, capable spacecraft is vast. Capability per satellite, not just cost per satellite, decides whether the math works.
But the patent is valuable precisely as a directional marker. It defines where satellite unit cost could go if manufacturing logic shifts from aerospace to semiconductors — and that floor is the number every constellation business is implicitly racing toward.